With new technologies that continue to shrink the feature size of integrated circuits into deep sub-micron domain, there is an increasingly higher incidence of sequence dependent defects during manufacturing. Two-pattern tests are therefore being used in manufacturing testing to supplement the traditional method of single pattern tests based on the stuck-at fault model. In this work we present methods of generating and applying two-pattern test sets to enable high quality and cost effective testing of sequence dependent defects such as transition delay faults, transistor stuck-open faults etc.